Lattice Semiconductor has announced their new low power, advanced system control FPGA family – the MachXO5T-NX. The MachXO5T-NX series FPGAs are based on the Lattice Nexus platform MachXO5T-NX improves upon previous generations with higher logic density, faster and advanced connectivity with PCIe interface, larger internal memory, and enhanced security features enabling more complex board management designs. MachXO5T-NX uses up to 2.5 times less power than similar class competitive devices while providing up to two times faster performance.
The new FPGA family features PCIe Gen 2 interfaces between the host processor and control FPGA. The embedded memory is up to 7.2Mb which is about 3.4 times more than most similar class FPGAs. Similarly, it also has increased dedicated user flash memory of 57Mb and hundred-time lower soft error rate other competing FPGAs. The 291 general purpose I/O’s support early I/O configuration and added features such as 1.25Gbps SGMII, default pull-down, hot socketing, and programmable slew rate, which enables simplified board designs. The advanced security features include On-chip multi-boot with bitstream encryption (AES256) and authentication (ECC256) and Run-time security capabilities not currently available in competitive FPGAs of a similar class.
MachXO5T-NX FPGAs are available for sampling and are supported by the latest release of Lattice Radiant design software.
